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Penn State University School of Electrical Engineering and Computer Science Page 1 of 8ProjectCMPEN 331 – Computer Organization and DesignDue Saturday, December 21, 2019 5:00 pm (Drop box on Canvas)Late submission is not accepted and will result in not getting any credits for the projectIn the project, you just need to implement what was decribed in the honor option section in lab 5, with the addition of theimplementation and generation of the bit stream without errors.1. Write a report that contains the following:i. Your Verilog design code. Use:i. Device: Zyboboard (XC7Z010- -1CLG400C)ii. Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file.iii. The waveforms resulting as requested from item 9 above.iv. The design schematics from the Xilinx synthesis of your design. Do not use any area constraints.v. Snapshot of the I/O Planning andvi. Snapshot of the floor planningvii. The design should be free from errors when synthesized, implemented and generated of the bitstream.The report format will be as follows:2. REPORT FORMAT: Free form, but it must be:a. One report per student.b. Have a cover sheet with identification: Title, Class, Your Name, etc.c. You have to write an abstract at the beginning of the project report to describe what you are doing in theproject.d. You should include an introduction for the project explaining with diagrams the connection between allthe stages and what would be the benefit of using that architecture in the computer organization field.e. Use Microsoft word and your report should be uploaded in word format not PDF. If you know LaTex,you should upload the Tex file in addition to the PDF file.f. Single spacedThe following part is not mandatory but any student will choose to do this part in addition to the previouspart, will take 5 points extra to the total grade of the course:In this extra points project, the students are implementing a pipeline CPU using the Xilinx design package for FPGAs. Youcan use any information available in previous labs if needed.3. PipeliningAs described in lab 34. Circuits of the Instruction Fetch StageAs described in lab 35. Circuits of the Instruction Decode StageAs described in lab 36. Circuits of the Execution StagePenn State University School of Electrical Engineering and Computer Science Page 2 of 8As described in lab 47. Circuits of the Memory Access StageAs described in lab 48. Circuits of the Write Back StageAs described in lab 59. Control Hazards and Delayed BranchThe control hazard occurs when a pipelined CPU executes a branch or jump instruction. The jump target address ajump instruction (jr, j, or jal) can be determined in the ID stage and it will be written into PC at the end of the IDstage. But because the pipelined CPU fetches instruction during every clock cycle, the next instruction is beingfetched during the ID stage of the jump instruction. The control hazard caused by a conditional branch instruction(beq or bne) becomes more serious than that of a jump instruction because the condition must be evaluated inaddition to the calculation of the branch of the target address. Figure 1 shows an example when we calculate thebranch target address in the EXE or the ID stage respectively. There are mainly two methods to deal with theinstruction(s) next to branch or jump instruction. One method is to cancel it (them). The other is to let it (them) beexecuted. The second method is called a delayed branch. The position in between the location of a jump or branchinstruction and the jump or branch target address are called delay slots. MIPS (microprocessor withoutinterlocked pipeline stages) ISA (instruction set architecture) adopts a one delay slot mechanism: the instructionlocated in delay slot is always executed no matter wither the branch is taken or not as shown in figure 2. In figure2 (a) shows the case where the branch is not taken. Figure 2 (b) shows the case where the branch is taken; t is thebranch target address. In both cases, the instruction located in a+4 (delay slot) is always executed no matterwhether the branch is taken or not. In order to implement the delayed branch with one delay slot, we must let theconditional branch instructions finish the executions in the ID stage. There should be no problem for calculatingthe branch target address within the ID stage. For checking the condition, we can perform an exclusive OR (XOR)on the two source operands:rsrtequ = ~| (da^db); // (da == db)where the rsrtequ signal indicates where da or db are equal or not. Both da and db should be the state ofthe art data. Referring to figures 3 and 4, we use the outputs of the multiplexers for internal forwarding as da anddb. This is the reason why we put the forwarding to the ID stage instead of to the EXE stage. Because thedelayed branch, the return address of the MIPS jal instruction is PC+8. Figure 5 illustrates the execution of thejal instruction. The instruction located in delay slot (PC + 4) was already executed before transferring control toa function (or a subroutine). The return address should be PC+8, which is written into $31 register in the WBstage by the jal instruction. The return form subroutine can be done by the instruction of jr $31. The jr rsinstruction reads the content of register rs and writes it into the PC.Figure 1 Determining whether a branch is taken or not taken(b) Branch is determined in ID stagebeq ID EXE? ? ? ??????ID EXEbeq ID? ? ? ??ID EXETarget address: ID EXE MEMTarget address: IFIFIF(a) Branch is determined in EXE stage .Penn State University School of Electrical Engineering and Computer Science Page 3 of 8Figure 2 Delayed branchFigure 3 Implementation with delayed branch with one delay slot(b) Branch is takena:a+4:a+8:a+12:a:a+4:t:t+4:beq IDID EXEbeq IDID EXEIF ID EXE MEMIF ID EXE MEM WBIF ID EXE MEMIF ID EXE MEM WBIF IF(a) Branch is not taken4clkIF IDopfuncControlunit fwdbfwdapcsrc rsrtequimmaddreqursrtEXEdadb0132013201324a doInstmempc rna qarnbqb dwnweRegfile<<<

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